The invention relates to digital frequency synthesizer (DFS) circuits for clocked digital systems. More particularly, the invention relates to a simple but flexible DFS circuit having particularly advantageous application to a Programmable Logic Device (PLD).
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBS, IOBS, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more programmable function blocks connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAS) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology.
Whatever type of architecture is used, PLDs generally include many programmable logic blocks of various types interconnected by a programmable interconnect structure. Other circuits included in the PLD might or might not be programmable. These additional circuits can include, for example, configuration logic and a clock distribution structure (clock tree).
FIG. 1 shows a typical PLD and the clock tree included in the PLD. The PLD includes a plurality of programmable logic blocks LB and an array or interconnect matrix (not shown) interconnecting the function blocks. In an FPGA, logic blocks LB correspond, for example, to IOBs or CLBs; in a CPLD, logic blocks LB correspond to function blocks or macrocells.
A PLD pad 101 is designated as the input clock pad, to which the system clock signal is supplied. The system clock signal is buffered (in inverting buffer 102) to reduce the capacitance of the system clock node, then is delivered to an approximate center point CP of the PLD. From center point CP, the clock signal is radially distributed to multiplexers M1-M4 and hence to inverting buffers B1-B4. The radial distribution equalizes the delay from the input clock pad 101 to the destination logic blocks LB.
The system clock signal is routed from center point CP to multiplexers M1-M4, which are individually controlled by configuration memory cells MC1-MC4 to pass either the system clock signal or a power high signal VDD. Each inverting buffer B1-B4 provides a selected signal to one quadrant of the PLD. Thus, if only a portion of the logic blocks are needed to implement a particular design, one or more quadrants can be left deliberately unused when logic is assigned to the logic blocks, and the corresponding multiplexer M1-M4 can be configured such that the corresponding clock buffer B1-B4 supplies the ground signal to the unused quadrant. In CMOS logic, power consumption is largely due to nodes changing state. Thus, grounding the clock signal for an entire quadrant of the device can potentially cut power usage of the PLD as a whole by as much as twenty-five percent.
FIG. 2 shows another prior art PLD, in which a further level of clock control is provided by including for each logic block a programmable clock buffer CB, interposed between inverting buffer B1-B4 and the input clock terminal of the logic block. Programmable clock buffer CB typically has the ability to select either the true or the complement clock signal for the logic block. Lo et al., in U.S. Pat. No. 6,456,126 B1, describe several such clock buffers, as well as several clock buffers having the additional capability of adding a programmable clock doubler function.
The PLDs of FIGS. 1 and 2 include programmable clock trees wherein the power consumption of the PLD can be reduced by disabling the clock signal for one or more quadrants of the device. However, this scheme is only effective if the design implemented in the PLD uses up to three-fourths of the PLD, which can require the purchase of a more expensive PLD than might otherwise be required. Further, all input and output pads for the design must then be mapped to portions of the PLD having an enabled clock signal, which can make board design more difficult. Therefore, it is desirable to provide PLDs having clock trees that offer alternative methods of reducing power consumption. It is further desirable to provide clock buffers offering programmable functions in addition to those described above.
The invention provides novel clock divider and digital frequency synthesizer (DFS) circuits that add little additional delay on the clock path. Each rising and falling edge of an input clock signal triggers a pulse from a pulse generator circuit. These pulses are passed to a control circuit. True and complement versions of the input clock signal are also provided to a multiplexer circuit. Under the direction of the control circuit, the multiplexer circuit passes selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the clock divider circuit. When neither the true nor the complement clock signal is passed by the multiplexer, a keeper circuit retains the value already present at the output clock terminal.
According to one embodiment of the invention, every Nth rising edge on the true clock signal is passed to the output terminal, where N is an even integer. Every Nth falling edge on the complement clock signal is also passed to the output terminal. This embodiment provides a divide-by-N output signal. In one embodiment, the selected edges are separated by N/2 rising edges. Thus, this embodiment provides a duty-cycle-corrected output clock signal.
The clock divider circuit of the invention provides the capability to divide by any even integer, rather than being limited to powers of two as are many clock dividers. The delay through the clock divider circuit is the same, regardless of which even number is selected as the divisor.
In one embodiment of the invention, the control circuit is implemented as a counter followed by a decoder circuit. In other embodiments, the control circuit is a state machine having at least four states. In a first state, the state machine enables the xe2x80x9ctruexe2x80x9d path through the multiplexer circuit and disables the xe2x80x9ccomplementxe2x80x9d path. In a second state, the state machine disables both paths through the multiplexer, and the next transition is to a third state. In the third state, the state machine enables the xe2x80x9ccomplementxe2x80x9d path through the multiplexer circuit and disables the xe2x80x9ctruexe2x80x9d path. In the fourth state, the state machine disables both paths through the multiplexer, and the next transition is to the first state. In the second and fourth states, the keeper circuit maintains the existing value on the output terminal of the clock divider circuit.
An advantage of this circuit is that many of the delays typical of prior art clock dividers (D-flip-flop delays, combinational logic delays, and so forth) are shifted from the clock path to the path through the control circuit. Therefore, these delays are not on the clock path, i.e., not on the critical path for the clock divider circuit.
Another advantage is that by controlling the functionality of the control circuit, any even number (up to the capacity built into the control circuit) can be selected as the divisor for the clock divider circuit. Therefore, the clock divider circuit of the invention provides additional flexibility compared to many known clock dividers.
In one embodiment, the described clock divider circuit is included in a programmable logic device (PLD). In some such embodiments, the control circuit is programmable to select a divisor from a group of supported divisors. The divisor selection can be controlled, for example, using configuration data stored in static RAM (SRAM) cells included in the control circuit.
According to another aspect of the invention, a digital frequency synthesizer (DFS) circuit is provided that includes a pulse generator circuit; a control circuit; first and second passgates controlled by the control circuit and passing a true and complement clock signal, respectively, to an output terminal of the DFS circuit; a keeper circuit coupled to the output terminal of the DFS circuit, and a ground control circuit. The ground control circuit has an input terminal coupled to the output terminal of the DFS circuit and is controlled by a signal on a ground select terminal. Thus, the DFS circuit can provide either a selected clock frequency, by using the control circuit to control the first and second passgates as described above, or a ground signal, by disabling the first and second passgates and enabling the ground select terminal.
In various embodiments, the functions supported by the control circuit can include any or all of the following functions: divide-by-two, divide-by-two with output edges aligned with rising edges of the true clock terminal, divide-by-two with output edges aligned with falling edges of the true clock terminal, multiply-by-two, output same as input, or output inverted from input. In other embodiments, the supported functions include division by an even number other than two.
In some embodiments, the DFS circuit includes a clock delay circuit coupled between the true clock input terminal and the control circuit. Some embodiments include means for selecting either the true or complement clock signal to be passed to the output terminal during power-up.
According to another aspect of the invention, a DFS circuit is provided that includes a true clock input terminal providing an input clock signal having a first frequency; a complement clock input terminal providing an input signal complementary to the input clock signal; an output clock terminal; first and second passgates passing the true and complement clock signals, respectively, to the output clock terminal; a keeper circuit coupled to the output clock terminal; and means for controlling the first and second passgates to provide an output clock signal having a second frequency to the output clock terminal.
In one embodiment, the second frequency is the same as the first frequency. In other embodiments, the second frequency is half or twice the first frequency. In some embodiments, the second frequency is the first frequency divided by an even number other than two. In some embodiments, a divided-down output clock signal can selectively have edges corresponding to either rising or falling edges of the input clock signal.
In some embodiments, the means for controlling the first and second passgates includes means for supplying disable signals to enable terminals of each passgate, and the DFS circuit includes means for providing a ground signal to the output clock terminal when the passgates are disabled. Thus, the output clock signal can be set to ground. In other embodiments, the DFS circuit includes means for providing a power high signal to the output clock terminal when the passgates are disabled.
The invention also provides a PLD in which the clock signal of each logic block can be selectively disabled. This PLD is an improvement over prior art PLDs, in which the clock can only be disabled for an entire quadrant of logic blocks. In a PLD according to this aspect of the invention, power savings can be applied to any design that uses less than all of the logic blocks in the PLD. Additionally, some embodiments provide various options, such as doubling or halving the clock frequency, that can now be selected on a per-logic-block basis. This capability reduces or eliminates the need to route various clock signals throughout the implemented design.
According to this aspect of the invention, a PLD includes a system clock input pad providing a system clock input signal; a clock buffer having an input terminal coupled to the system clock input pad and further having an output terminal; a central node coupled to the output terminal of the clock buffer; a plurality of secondary clock buffers each having an input terminal coupled to the central node and each further having an output terminal; a plurality of programmable logic blocks divided into sets, each set of programmable logic blocks having an associated secondary clock buffer, each programmable logic block having an input clock terminal; and a plurality of synthesizer circuits coupled between the output terminals of the secondary clock buffers and the input clock terminals of associated programmable logic blocks. Each synthesizer circuit includes means for selectively decoupling the input clock terminals of the programmable logic blocks from the output terminals of the secondary clock buffers and providing a steady-state signal to the input clock terminals of the programmable logic blocks.
Some embodiments also support the capability of selectively deriving an output clock signal according to desired characteristics, such as frequency, rising or falling edge alignment, and so forth. Some such embodiments include means for selectively deriving an output clock signal from an input clock signal on the output terminal of the associated secondary clock buffer and providing the output clock signal to the input clock terminal of the associated programmable logic block.